module WRAP_FIFO8K_64_64(
   RESET,
   WR_CLK,
   RD_CLK,
   DIN,
   WR_EN,
   RD_EN,
   DOUT,
   FULL,
   EMPTY
   );


input          RESET;
input          WR_CLK;
input          RD_CLK;
input[63:0]    DIN;
input          WR_EN;
input          RD_EN;
output[63:0]   DOUT;
output         FULL;
output         EMPTY;

XILINX_V6_FIFO8K_64_64    INST_FIFO8K_64_64(
   .rst        ( RESET ),
   .wr_clk     ( WR_CLK ),
   .rd_clk     ( RD_CLK ),
   .din        ( DIN[63:0] ),
   .wr_en      ( WR_EN ),
   .rd_en      ( RD_EN ),
   .dout       ( DOUT[63:0] ),
   .full       ( FULL ),
   .empty      ( EMPTY )
   );

endmodule 


